FLIP - Field-programmable Logic and Interconnect Project

FLIP is a project for Stanford's EE272A VLSI projects course.

The FLIP project's goal is to design and test an FPL (Field-Programmable Logic) chip. The design is similar in organization to other so-called FPGA designs. However, we are experimenting with a novel type of CLB (Combinational Logic Block) which has never been implemented in a fabricated device before.

FLIP Resources

• I know that some Ghostviews have a problem with the following document. (Mine included.) But it seems to print ok for me on the printer. Try the PDF which, for some unknown yet amusing reason, is in page-reverse order!
• FLIP Draft Design Proposal [ PostScript] [ FrameMaker] [ PDF]
• The Java source for a basic technology mapping tool for our CLBs.
• The Java source for another class used to model the input pins to the CLB.
• The Java source that models the CLB.
• The Verilog code for the SRAM/Interconnect array: SI_array.v
• The Perl code that generates the Interconnect Verilog: make_interconnect.pl
• The configuration of the Interconnect for the Perl script: connections
• CVS Logs for Magic layout.
• CVS Logs for Verilog model.
• CVS Logs for Tests.
• CVS Logs for Documents.